Semiconductor integrated circuit devices are typically fabricated by a layering process in which several layers of material (e.g. a dielectric and a metal such as copper) are fabricated (i) on a surface of a semiconductor wafer, or (ii) on a surface of a previous layer. This fabrication process very often requires layers to be fabricated upon a smooth, planar surface of a previous layer. However, the surface topography of layers may be highly uneven due to (i) areas which are higher than the remainder of the surface or (ii) an uneven topography of an underlying layer. As a result, a layer may need to be polished so as to present a smooth planar surface for the next processing step, such as formation of a conductor layer or pattern on the surface of another layer.
In general, a semiconductor wafer may be polished to remove high topography and surface defects such as crystal lattice damage, scratches, roughness, or embedded particles of dirt or dust. The polishing process typically is accomplished with a polishing system that includes top and bottom platens (e.g. a polishing table and a wafer carrier or holder), between which the semiconductor wafer is positioned. The platens are moved relative to each other thereby causing material to be removed from the surface of the semiconductor wafer to a desired end point. This polishing process is often referred to as mechanical planarization (MP) and is utilized to improve the quality and reliability of semiconductor devices. The polishing process may also involve the introduction of a chemical slurry which may chemically react with the surface of the semiconductor wafer so as to facilitate higher removal rates of materials fabricated upon the semiconductor wafer. This polishing process is often referred to as chemical mechanical planarization or chemical mechanical polishing (CMP).
Once the CMP is completed the wafer surface is rinsed with an aqueous solution in an attempt to wash away material left there by the CMP process (e.g. slurry residue and/or other reaction products). Subsequent to the rinse, the semiconductor wafer surface is also scrubbed with a brush in the presence of water in an attempt to further remove any material left there by the CMP process which is trapped in tiny crevices or channels defined in the surface of the wafer. Once the rinse and scrub procedures are completed the deposition of an additional material onto the polished surface of the semiconductor wafer can take place. The above described procedure is then repeated until the desired multi-layer structure is obtained.
A drawback to the above described fabrication procedure is that the rinsing and brushing procedures can fail to remove a sufficient amount of the material left on the surface of the semiconductor wafer by the CMP process. Failing to remove a sufficient amount of the material left on the surface of the semiconductor wafer by the CMP process can result in yield and/or reliability problems for thereafter fabricated semiconductor integrated circuit devices.
Thus, a continuing need exists for an arrangement and method which efficiently removes CMP residue and/or other reaction products from a surface of a semiconductor wafer.